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活動名稱 Fan-Out Wafer/Panel-Level Packaging for 3D IC Heterogeneous Integration
活動日期 2018-06-25
地  點 工研院中興院區51館422會議室
主辦單位 先進微系統與構裝技術聯盟(AMPA)
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報名截止日期 2018-06-20
聯絡窗口 ※聯絡窗口: TEL: (03)591-7408 ,Email:alantsai@itri.org.tw TEL: (03)591-9053 ,Email:yyhsieh@itri.org.tw
講  師 ※講師:劉漢誠博士(Dr. John H. Lau) ASM, HK 852-2619-2757, john.lau@asmpt.com

Brief BIO
With more than 39 years of R&D and manufacturing experience in semiconductor packaging, John has published more than 470 peer-reviewed papers, 30 issued and pending US patents, and 19 textbooks on, e.g., Advanced MEMS Packaging (McGraw-Hill Book Company, 2010), Reliability of RoHS compliant 2D and 3D IC Interconnects (McGraw-Hill Book Company, 2011), TSV for 3D Integration, (McGraw-Hill Book Company, 2013), 3D IC Integration and Packaging (McGraw-Hill Book Company, 2016), and Fan-out Wafer-Level Packaging (Springer, 2018). John is an elected ASME Fellow and has been an IEEE Fellow since 1994.
 

ABSTRACT

Because of the drive of Moore’s law, SoC (system-on-chip) has been very popular in the past 10+ years. Unfortunately, the end of Moore’s law is fast approaching and it is more and more difficult and costly to reduce the feature size (to do the scaling) to make the SoC. Heterogeneous integration contrasts with SoC. Heterogeneous integration uses packaging technology to integrate dissimilar chips with different functions into a system or subsystem. For the next few years, we will see more implementations of a higher level of heterogeneous integration, whether it is for time-to-market, performance, form factor, power consumption or cost. Fan-out wafer-level packaging (FOWLP) has been getting lots of tractions since TSMC used their FOWLP to package the application processor for the iPhone 7. In this lecture, the following topics will be presented and discussed. Emphasis is placed on the latest developments of these areas in the past three years. Their future trends will also be explored.



【議  程】

Lecture Outlines

[1] Patents Impacting the Semiconductor Packaging

[2]Formation of Fan-out Wafer-Level Packaging (FOWLP)

Ø FOWLP Chip-first (die face-down)

Ø FOWLP Chip-first (die face-up)

Ø FOWLP Chip-last (RDL-first)

[3]Fabrication of Redistribution Layers (RDLs)

Ø Polymer and ECD Cu + Etching

Ø PECVD and Cu damascene + CMP

Ø Hybrid RDLs

[4]TSMC InFO-WLP and InFO-PoP

[5]Formation of Fan-out Panel-Level Packaging (FOPLP)

Ø PCB + SAP

Ø PCB + LDI

Ø PCB + TFT-LCD

Ø PCB/ABF/SAP + LDI

[6]Wafer vs. Panel

Ø Application Ranges of FOWLP and FOPLP

Ø Critical Issues of FOPLP

[7] Embedded Chips Panel-Level Packaging (ECP)

Ø TI/AT&S

Ø TDK

Ø Fujikura

Ø Schweizer

[8]Notes on Dielectric and Epoxy Molding Compound

[9] System-on-Chip (SoC)

Ø Apple’s application processor (A10)

Ø Apple’s application processor (A11)

[10] Heterogeneous Integration vs. SoC

[11] Heterogeneous Integration on Organic Substrates (SiP)

Ø Amkor’s SiP for automobiles

Ø Apple Watch II assembled by ASE

Ø Intel’s Knights-Landing with Micron’s HMC on Organic Substrate

Ø Cisco/eSilicon’s Networking system on Organic Interposer

[12] Heterogeneous Integration on Silicon Substrates (TSV-Interposers)

Ø Leti’s system-on-wafer (SoW)

Ø UCLA’s SoW

Ø TSMC/Xilinx’s CoWoS

Ø AMD’s GPU with Hynix’s HBM and UMC’s TSV-interposer

Ø NVidia’s GPU with Samsung’s HMB2 and TSMC’s TSV-interposer

[13] Heterogeneous Integration on RDLs and/or TSV-less Interposers

Ø Xilinx/SPIL’s TSV-less SLIT

Ø SPIL/Xilinx’s TSV-less NTI

Ø Amkor’s TSV-less SLIM

Ø Amkor’s TSV-less SWIFT

Ø Amkor’s TSV-less SLIM with FOWLP

Ø SPIL’s TSV-less FOWLP with Hybrid RDLs

Ø STATS ChipPac’s FOFC eWLB

Ø ASE’s TSV-less FOCoS

Ø MediaTek’s TSV-less RDLs by FOWLP

Ø Intel’s TSV-less EMIB

Ø Intel/AMD’s TSV-less EMIB for CPU, GPU, and HBM

Ø 3D IC Heterogeneous Integration for Application Processor Chipset

Ø 3D IC High-Performance Heterogeneous Integration

Ø Samsung’s Heterogeneous Integration on RDLs

Ø Assembly of Heterogeneous Integration

[14] FOW/PLP and Heterogeneous Integration Trends

[15] Summary

[16] Q&A

 
 
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