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活動名稱 Recent Advanced and Trends in Fan-Out Wafer/Panel-Level Packaging and Heterogeneous Integrations
活動日期 2019-08-26
地  點 工研院中興院區51館422會議室 (新竹縣竹東鎮中興路四段195號)
主辦單位 工研院電光所/先進微系統與構裝技術聯盟
協辦單位 材化所
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報名截止日期 2019-08-20
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附件檔案    報名表
講  師 John H Lau
Unimicron Technology Corporation
886-3350-0386 ext:11118; John_Lau@Unimicron.com
 

Fan-out wafer/panel-level packaging (FOW/PLP) has been getting lots of tractions since TSMC used their InFO to package the application processor for the iPhone 7. In this lecture, the following topics will be presented and discussed. Emphasis is placed on the latest developments of these areas in the past few years. Their future trends will also be explored. Heterogeneous integration uses packaging technology to integrate dissimilar chips, photonic devices, and/or components (side-by-side and/or stack) with different materials and functions, and from different fabless design houses, foundries, wafer sizes, feature sizes and companies into a system or subsystem. For the next few years, we will see more implementations of FOW/PLP and a higher level of heterogeneous integrations, whether it is for time-to-market, performance, form factor, power consumption or cost. Some of the ECTC2019 and SEMICON West papers will also be presented.

 



【議  程】
CONTENTS
[1] Introduction 
[2] Formation of Fan-out Wafer-Level Packaging (FOWLP)
FOWLP Chip-first (die face-down)
FOWLP Chip-first (die face-up)
FOWLP Chip-last (RDL-first)
[3] Fabrication of Redistribution Layers (RDLs)
Polymer and ECD Cu + Etching
PECVD and Cu damascene + CMP
Hybrid RDLs
ABF/LDI and PCB Cu-plating + Etching
[4] Warpages
Kinds of Warpages
Allowable of Warpages
[5] Reliability of FOWLP
Thermal-Cycling Test
Thermal-Cycling Simulations
Drop Test
Drop Simulations
[6] TSMC InFO
InFO-PoP
InFO_AiP/RF-Chip Driven by 5G
InFO for HBM (High Bandwidth Memory)
[7] Samsung PLP
PoP for Smartwatches
SiP SbS for Smartphones
[8] Formation of Fan-out Panel-Level Packaging (FOPLP)
PCB + SAP
PCB + LDI
PCB + TFT-LCD
PCB/ABF/SAP + LDI
[9] Wafer vs. Panel 
Application Ranges of FOWLP and FOPLP
Critical Issues of FOPLP
[10] Fan-Out RDL for High Performance Applications
STATSChipPac’s FOFC-eWLB
ASE’s FOCoS
MedieTed’s FO-RDLs
Samsung’s Si-Less RDL Interposer
TSMC’s InFO_oS
[11] Trends in FOWLP and FOPLP
[12] System-on-Chip (SoC)
[13] Heterogeneous Integrations or SiPs
[14] Heterogeneous Integrations vs. SoC
[15] Heterogeneous Integrations on Organic Substrates
[16] Heterogeneous Integrations on Silicon Substrates (TSV-Interposers)
[17] Heterogeneous Integrations on Silicon Substrates (TSV-less Interposers, e.g., Bridges)
[18] Heterogeneous Integrations on Fan-Out RDL Substrates
[19] Heterogeneous Integration of PoP (package-on-package)
[20] Heterogeneous Integration of Memory Stacks
[21] Heterogeneous Integration of Chip-to-Chip Stacks
[22] Heterogeneous Integration of CIS (CMOS Image Sensor) and Logic Chip
[23] Heterogeneous Integration of LED (light-emitting diode) and TSV-Interposers
[24] Heterogeneous Integration of MEMS (microelectromechanical systems) and Logic Chip
[25] Heterogeneous Integration of VESCL (vertical cavity surface emitted laser) and PD (photodiode)
[26] Trends in Heterogeneous Integrations
[27] Some ECTC2019 and SEMICON West Papers
TSMC’s SoIC for Heterogeneous Integrations
TSMC’s 3D-MiM Fan-Out Wafer-Level Packaging
ASE’s FOWLP for AiP/RF-Chip Driven by 5G
ASE’s FOCoS with Chip-Last Formation
ASE’s 300mmx300mm Panel-Level Fan-Out Packaging
SPIL’s FOWLP with 350mm Solder Ball Pitch
IME’s FOWLP for Ultra-Thin PoP
Imec/Brewer Science’s Bridge + TPV +FOWLP
Toshiba’s FOWLP with Photosensitive Through Mold Vias
Intel’s 0.3mm Pitch Solder Balls WLP
Intel’s co-EMIB (Embedded Multi-Die Interconnect Bridge)
Intel’s ODI (Omni-Directional Interconnect)
Intel’s MDIO (Management Data Input/Output)
 
 
 
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10724kb .pdf 2019/11/19
10441kb .pdf 2019/11/19

 
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