There are two portions of this lecture. The first half is for the recent advances of 3D IC integration and the materials are based on the Proceedings of the conferences such as IEEE/IEDM and IEEE/ISSCC. The second half is for the recent advances of advanced packaging which has been supporting the mobile products such as the smartphones and tablets and will be the main driver for materials consumption and new materials development for the wearable products such as smartwatch. The objective of this half-day lecture is to systematically share with you the latest research and developments in design, materials, process, equipments, manufacturing, test, characterization and reliability of 3D IC integration and advanced packaging.

Lecture Outlines

1.         Introduction

2.         STMircoelectronics 3D stack CMOS image sensor with TSV

3.         SONY’s 3D stack CMOS image sensor with TSV

4.         Tohoku University’s Super-Chip with TSVs

5.         IME’s TSV Cu pumping and solution

6.         IMEC’s TSV Cu pumping and solution

7.         University of Taxis’ Cu TSV keep out zone

8.         IMEC’s Cu TSV induced keep-out-zone for 10nm FinFET CMOS technology

9.         JCAP’s wafer-level LED with TSVs

10.    Huazhong University’s LED with TSVs

11.    Avago’s FBAR (MEMS) with TSVs

12.    IME’s MEMS with TSVs

13.    IZM’s MEMS with TSVs

14.    IMEC’s MEMS with TSVs

15.    3D Memory chips stacking by wirebonding

16.    3D Package-on-Package (PoP)

17.    3D chip-to-chip and face-to-face interconnects

18.    Package substrate with build-up layers for flip chips

19.    Package substrate with thin-film layers on top of the build-up layer

20.    Coreless substrate

21.    Fan-in wafer-level package (WLP)

22.    Fan-out embedded wafer-level package (eWLP)

23.    3D eWLP in PoP format

24.    3D eWLP in face-to-face format

25.    Embedded chip in SiP rigid substrate

26.    Embedded chip in SiP flexible substrate

27.    Embedded 3D stack chips in SiP flexible substrate

28.    Summary

29.    Q&A