Recent advances in, e.g., fan-out wafer/panel level packaging (TSMC’s InFO-WLP and Fraunhofer IZM’s FO-PLP), 3D IC packaging (TSMC’s InFO_PoP vs. Samsung’s ePoP), 3D IC integration (Hynix/Samsung’s HBM for AMD/NVIDIA’s GPU vs. Micron’s HMC for Intel’s Knights Landing CPU), 2.5D IC Integration (TSV-less interconnects and interposers),  embedded 3D hybrid integration (of  VCSEL, driver, serializer, polymer waveguide, etc.), and 3D MEMS/IC integration will be discussed in this presentation. Emphasis is placed on various FOWLP formation methods such as chip-first with die-up, chip-first with die-down, and chip-last (RDL-first). Since RDLs (redistribution layers) play an integral part of FOWLP, various RDL fabrication methods such as Cu damascene, polymer, and PCB (printed circuit board) will be discussed. A few notes and recommendations on wafer vs. panel, dielectric materials, and molding materials will be provided. Also, TSV-less interposers such as those given by Xilinx/SPIL, Amkor, ASE, Intel, ITRI, and Shinko will also be discussed.

Lecture Outlines

(A) Introduction

(B) Fan-Out Wafer/Panel-Level Packaging

(1) Patents Impacting the Semiconductor Packaging

(2) Fan-out Wafer/Panel-Level Packaging Formations

Ø Chip-first (die-down)

Ø Chip-first (die-up)

Ø Chip-last (RDL-first)

(3) RDL Fabrications

Ø Polymer method

Ø PCB/LDI method

Ø Cu damascene method

(4) TSMC InFO-WLP

(5) TSMC InFO-PoP vs. Samsung ePoP

(6) Wafer vs. Panel Carriers

(7) Notes on Dielectric and Epoxy Mold Compound

(8) Semiconductor and Packaging for IoTs (SiP)

(9) Wafer-Level System-in-Package (WLSiP)

(10) Package-Free LED (Embedded LED CSP)

     (C) 3D IC Integration

           (1) Memory Chip Stacking – Samsung’s DDR4 with TSVs

           (2) Hybrid Memory Cube (HMC) – Intel’s Knights Landing

           (3) High Bandwidth Memory (HBM) – Hynix/AMD’s GPU

           (4) Samsung’s Widcon

           (5) 3D IC/MEMS Integration

           (6) Embedded 3D Hybrid Integration

      (D) 2.5D IC Integration and TSV-Less Interposers

           (1) TSMC/Xilinx’s CoWoS

           (2) Xilinx/SPIL’s TSV-less SLIT

           (3) Amkor’s TSV-less SLIM

           (4) ASE’s TSV-less FOCoS

           (5) Intel’s TSV-less EMIB

           (6) ITRI’s TSV-less TSH

           (7) Shinko’s TSV-less i-THOP

      (E) Semiconductor Packaging New Trends

      (F) Summary and Q&A